1. Field of the Invention
The present invention is related to integrated circuit (IC) design and, more particularly, to designing and fabricating ICs in three dimensions (3D).
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important but, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
To minimize semiconductor circuit power consumption, most integrated circuits (ICs) are made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS. A typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. A CMOS inverter, for example, is a PFET and NFET pair that are series connected between a power supply voltage (Vdd) and ground (GND). Both are gated by the same input and both drive the same output, typically a capacitive load and, ideally, a typical CMOS circuit consumes only transient or switching power.
The typical approach to improving density (more FETs per unit area) has been to shrink minimum design dimensions. However, this approach is always limited by those minimum dimensions. For added density chips can be stacked to double, triple and etc. device density in what may be termed a three dimensional (3D) chip. However, simply stacking chips requires maintaining the normal chip circuit boundaries. So signals passing between chip boundaries still suffer the penalties attributed to inter-chip communications. By contrast, in what may be termed a rudimentary top down approach, layers of FETs, e.g., alternating layers of PFETs and NFETs, are formed individually and bonded on top of one another to form a 3D IC chip. For example, Kunio et al., entitled “Three Dimensional ICs, Having Four Stacked Active Device Layers,” IEEE, 1989, describes forming such a top down CMOS chip with polysilicon interconnects connecting the FETs on adjacent layers into circuits. In this example, a CMOS static random access memory (SRAM), programmable logic array (PLA), and CMOS gate array for I/O buffers are included on the same 3D IC chip. Polysilicon has inherent resistance that may be ignored for short distances, e.g., cross coupling SRAM cell inverters, but adds delay when driving a load of any significance (i.e., the polysilicon connection resistance from a driver driving a large capacitive load combines to add an RC delay to the path) and long polysilicon wire runs act as a distributed RC which also adds a distributed delay.
In state of the art top down 3D chips, however, individual circuits/macros are assembled or placed on one or more various circuit layers. Each of the circuit layers may include local wiring to wire devices together into circuits (e.g., AND, OR, NAND, NOR gates) and, in some cases, to wire circuits together into higher order functions (e.g., an n bit by n bit multiplier) or macros. The circuit layers are joined to form a single multilayered 3D chip. However, if the circuit layers are improperly or imprecisely aligned, chip functions may fail. Further, wiring on one layer can interfere electrically with wiring on another, e.g., through cross talk or because a signal cannot be routed between layers. So, typically, strict wiring constraints are necessary to avoid wiring problems and to adequately allocate wiring resources between the circuit layers. Furthermore, structures and systems must, of necessity, optimize wiring resources. Optimal logic and memory structure partitioning and placement is not well understood for these types of top down layered chips. Further, as noted above, timing problems can arise during logic partitioning for stacked macros. So, it may be impossible after placement and partitioning to close on the design, e.g., from the point of view of timing, thermal issues and/or noise. Finally, designing random logic in multiple layers can be very expensive, requiring special tools and much more complex simulations.
In what is sometimes termed a bottom up approach, after the design for one layer of circuits is completed with macro/layer inputs and outputs (I/Os) set, the design for the next layer begins. So, for example, circuits are fabricated conventionally on the lowest layer, e.g., on bulk silicon substrate or a silicon surface layer of a silicon on insulator (SOI) wafer. Then, a second circuit layer is formed (e.g., epitaxial silicon (epi Si) growth, recrystallization of amorphous silicon, or wafer bonding) on the base wafer and device processing is completed on that second layer. Thereafter, the sequence may be repeated to create additional superstructure circuit layers. Generally, once place and wire is complete for a circuit layer subsequent design considerations (e.g., selectively powering up logic gates as a result of timing analysis), the layer may, necessarily, be re-placed and re-wired if insufficient space remains, e.g., for powering up buffers. Furthermore, FETs formed in upper layers of bottom up 3D chips are of poor quality and degrade circuit performance. In addition, because forming the upper layers thermally cycles previously formed lower layers, sequentially forming subsequent circuit layers also degrades characteristics of the bottom, base circuit layer. For example, thermal cycling can cause dopant to diffuse from a well defined source/drain into adjacent channel regions, which degrades performance even for those circuits that do not include devices in layers other than the base circuit layer. As a result, material choices are limited for bottom up designs and, although very high density chips may be formed, FET quality is incompatible with high performance.
Thus, there is a need for very dense high performance integrated circuits and a method of designing such circuits such that circuit function may be distributed amongst a number of circuit layers without adversely impacting circuit performance.